Questions
Syllabus
Qns. By Syllabus

Semester

Subject

Year

Tribhuwan University

Institute of Science and Technology

Model

Bachelor Level / First Year / First Semester / Science

Bachelors in Information Technology (BIT103)

(Digital Logic)

Full Marks: 60

Pass Marks: 24

Time: 3 Hours

Candidates are required to give their answers in their own words as for as practicable.

The figures in the margin indicate full marks.

Section A

Long Answers Questions

Attempt any TWO questions.
[2*10=20]
1.
Design the full adder circuit using 3 to 8 decoder and explain the working principle. [10]
2.
What is JK master slave flip-flop? Design its logic circuit, truth table and explain the working principle. [10]
3.
The term LOGIC GATES is to be transmitted as 12 bytes of data. Each character in the term has an ASCII value. The system uses odd parity and left most bit is used as parity bit. An additional parity byte is also sent after the term. The following bytes have arrived at their destination. a. One of the bytes has an error after transmission. Locate which character contains an error. b. Locate the bit that has been transmitted incorrectly. c. Explain how you have arrived at your conclusion.
letters123456781L010011002O010011113G110001114I010010015C010000116⟨space⟩001110107G110001118A110001019T0101100010E0100010111S0101011112Parity byte01001111\begin{array}{|c|c|c|c|c|c|c|c|c|c|}\hline & \text{letters} & 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 \\ \hline 1 & L & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 \\ 2 & O & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\ 3 & G & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ 4 & I & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 \\ 5 & C & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\ 6 & \langle \text{space} \rangle & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 \\ 7 & G & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ 8 & A & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 1 \\ 9 & T & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 \\ 10 & E & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 \\ 11 & S & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 1 \\ 12 & \text{Parity byte} & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\ \hline \end{array}
[10]
Section B

Short Answers Questions

Attempt any Eight questions.
[8*5=40]
4.
Show that the dual of the exclusive-OR is equal to its complement. [5]
5.
Explain with state diagram and excitation table for 3-bit binary counter. [5]
6.
Design a decoder with three input lines but with only six output lines. If the value of the input corresponds to 6 or 7, then all output line should be asserted to signal an error. [5]
7.
What are the special characteristics of IC digital logic family? Explain them in brief. [5]
8.
A logic circuit implements the following Boolean function. F=A'C+AC'D It is found that the required input combination A=C=1 can never occur. Using K-map and proper don't care condition find simpler expression for F and implement it using not gate only. [5]
9.
a) Obtain the 9's and 10's complement of i) 13579 ii) 90090 decimal number. b) Convert 6524275 octal to hexadecimal [5]
10.
Design 8 to 1 Multiplexer using two 4to 1 Multiplexers. [5]
11.
Given is a logic (switching) function F1 in the decimal list sum-of-minterms representation. F1(A,B,C,D)=Σ(0,2,3,5,7)F_1(A,B,C,D) = \Sigma(0, 2, 3, 5, 7) , d(A,B,C,D)=Σ(8,10,13,15)d(A,B,C,D) = \Sigma(8, 10, 13, 15) [5]
12.
Write short notes on: PLA Write short notes on Triggering of flip-flop [2.5+2.5]