Questions
Syllabus
Qns. By Syllabus

Semester

Subject

Year

Bachelors Level/First Year/First Semester/Science csit/first semester/digital logic/syllabus wise questions

B.Sc Computer Science and Information Technology

Institute of Science and Technology, TU

Digital Logic (CSC116)

Year Asked: 2075, syllabus wise question

Binary Systems
1.
Convert the following decimal numbers to the indicated bases. a) 7562.45 to octal b) 1938.257 to hexadecimal c) 175.175 to binary [2+1.5+1.5]
Combinational Logic
1.
Implement the following function F using: a. Decoder b. Multiplexer c. PLA [4+2+2+2]
2.
Design a combinational circuit with three inputs, x, y and z, and three outputs, A, B and C. When the binary input is 0,1,2, or 3, the binary output is one greater than the input. When the binary input is 4,5,6 or 7, the binary output is one less than the input. [5]
Combinational Logic with MSI and LSI
1.
The following is a truth table of a 3-input, 4-output combinational circuit. Tabulate the PAL programming table for the circuit and mark the fuses to be blown in a PAL diagram.
InputsOutputsXYZABCD00001000011111010101101101011001010101000111011101110111\begin{array}{|c|c|c|c|c|c|c|c|}\hline \text{Inputs} & & & \text{Outputs} & & & \\ \hline \text{X} & \text{Y} & \text{Z} & \text{A} & \text{B} & \text{C} & \text{D} \\ \hline 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 1 & 1 & 1 & 1 & 1 \\ 0 & 1 & 0 & 1 & 0 & 1 & 1 \\ 0 & 1 & 1 & 0 & 1 & 0 & 1 \\ 1 & 0 & 0 & 1 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 \\ 1 & 1 & 1 & 0 & 1 & 1 & 1 \\ \hline \end{array}
[4]
2.
Implement half adder using 2-4 decoders. [5]
3.
Design the priority encoder circuit. [5]
Registers and Counters
1.
What is the difference between a serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed? [5]
2.
Design a 4-bit binary ripple counter with D flip-flops. [5]
Simplification of Boolean Functions
1.
Express the Boolean function F = A+B'C in a sum of minterms. [5]
2.
Reduce the following function using k-map. F=B'D+A'BC'+AB'C+ABC' [5]
Synchronous and Asynchronous Sequential Logic
1.
Design clocked sequential circuit of the following state diagram by using JK flip-flop.
question image
[4]
2.
Write short notes on (any two): a. SIMM b.RTL c.Parity Checker [5]