Questions
Syllabus
Qns. By Syllabus

Semester

Subject

Bachelors Level/Fourth Year/Seventh Semester/Science csit/seventh semester/digital system design/syllabus

B.Sc Computer Science and Information Technology

Institute of Science and Technology, TU

Nature of the course: (Theory+Lab)

F.M: 60+20+20 P.M: 24+8+8

Credit Hrs: 3Hrs

Digital System Design [CSC427]
Course Objective
i.
The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.
Course Description

This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification

S1:S1[5]
1
Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing, Logic Families, IC Design Techniques, IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices
S2:S2[4]
1
Review of Boolean Algebra and Combinational Logic, Canonical Form, Shannon's Expansion, Minterms, Maxterms, Prime Implication
S3:S3[5]
1
Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR), Standard Combinational Networks
S4:S4[7]
1
Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method, PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA), Gate Arrays, Programmable Gate Array, Full Custom Design
S5:S5[8]
1
Sequential Networks: Transition from combinational to sequential network, Direct command flip flop, Initialization of sequential network, Level Enabled Flip-Flops, Synchronization of sequential networks, Edge-triggered Flip Flops, Synchronous and Asynchronous Signals
S6:S6[6]
1
Sequential Networks as Finite State Machines: Standard Models, Realization with ASM Diagrams, Synthesis of Synchronous FSM, Time Behavior of Synchronous FSM, Design of input forming, Logic and Output Forming Logic of state machine.
S7:S7[4]
1
Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA
S8:S8[6]
1
Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing, Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability
References
1.
Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita, Introduction to Digital System Design, Springer
2.
Wolf, Wayne, Modern VLSI Design-System on Silicon, Third Edition, Pearson
3.
Comer, David J. Digital Logic State Machine Design, Third Edition, Oxford University Press
4.
Ashenden, Peter J, The Student's Guide to VHDL, Morgan Kaufman
Labrotary Work
Laboratory Exercise should cover the implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.